Today's complex integrated circuits such as a system on a chip (SOC) need a considerable number of blocks to be initialized before the SOC can begin to perform its intended operation. Initialization time has a two-fold impact on SOC performance. One impact relates to the delay in commencing of the actual SOC functionality. For instance, several systems require the SOC to respond in a time bound manner after the power on. In such systems, the delay (e.g., waiting for circuit reset) in commencing actual functionality is detrimental. Another impact during initialization relates to consumption of power while the internal modules of the SOC are being configured.
In some systems, such as WLAN and Bluetooth, the power consumed during the initialization phase is significant where a typical SOC may contain several hundred registers which need initialization at reset. For example, a given application SOC may contain over 8000 bits for radio frequency (RF) configuration alone. This is apart from the large number of registers within various SOC modules. At the time of initial testing of the SOC, register reset values are not known and thus could change significantly in later SOC versions. This requires either the processor to change register contents (which consumes time/power), or an integrated circuit change in which the reset functionality is changed via multi-level mask changes which can cost hundreds of thousands of dollars.